module serializer_10b(
    input          resetn,
    // 数据输入时钟
    input          dclk,
    // 串行时钟
    input          serclk,
    input  [9:0]   din,
    output         dout
);
// 拆分上升沿与下降沿的数据
wire [4:0] drise = {din[8],din[6],din[4],din[2],din[0]};
wire [4:0] dfall = {din[9],din[7],din[5],din[3],din[1]};
reg  [9:0] din_q;
reg  [4:0] drise_s;
reg  [4:0] dfall_s;

always @(posedge dclk or negedge resetn) begin
    if(!resetn) begin
        din_q <= 10'b0;
    end
    else begin
        din_q <= din;
    end
end
// 计数并按时钟顺序输出
reg [2:0] cnt;
always @(posedge serclk or negedge resetn) begin
    if(!resetn) begin
        cnt <= 3'b0;
        drise_s <= 5'b0;
        dfall_s <= 5'b0;
    end
    else begin
        cnt <= cnt[2] ? 3'd0 : cnt + 3'd1;
        drise_s <= cnt[2] ? drise : {1'b0, drise_s[4:1]};
        dfall_s <= cnt[2] ? dfall : {1'b0, dfall_s[4:1]};
    end
end

ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"), // 仅上升沿采样
    .INIT(1'b0),
    .SRTYPE("SYNC")
) ODDR_inst (
    .Q(dout),
    .C(serclk),
    .CE(1'b1),
    .D1(drise_s[0]),       // 上升沿数据
    .D2(dfall_s[0]),       // 下降沿数据
    .R(~resetn),
    .S(1'b0)
);
endmodule